The present invention relates to a wireless communication calibration system, and more particularly, to a calibration system that measures a delay outside chipset for calibration, and an associated method.
The performance of various radio features, such as the timing accuracy of packets at an antenna port in the 802.11 v/mc standard or the phase delay at multiple antenna ports for beam-form support in the 802.11 standard, is affected by the accuracy of a measured circuit delay to a resolution of nanoseconds. Delay of analog circuits outside the chipset, such as a Film Bulk Acoustic Resonator (FBAR) filter or Bulk Acoustic Wave (BAW) filter, may have a variation of tens of nanoseconds among chip samples, or as a result of operation frequency or changes in temperature. Therefore, the estimation of circuit delay on both the transmitter and receiver path, including both digital and analog circuits inside and outside the chip, to a resolution of nanoseconds in order to calculate or control timing of packets transmitted or received at the antenna port is a problem which needs to be solved. Conventional methods for calibrating circuit delay such as using a look-up table requires large memory resources, as a calibration table with various dimensions such as temperature, frequency and component vendors needs to be stored. This also consumes time for applying offline calibration. In addition, employing a calibration loop inside the chipset cannot compensate for the circuit delay outside the chipset.